This invention relates to memory systems and, in particular, to semiconductor memories in which the wire connections needed to control and/or test selected functions are reduced.
A problem solved by the present invention is best explained with reference to the prior art scheme shown in FIG. 1. FIG. 1 shows a portion of a dynamic random access memory (DRAM), 10, formed on a single integrated circuit (IC) or chip. The DRAM 10 includes a voltages generator block 12 which under the control of a controller 14 is used to generate many of the different voltages (e.g., operating, bias and reference voltages) needed to operate various circuits on the chip. As outlined in FIGS. 1 and 2, the voltages generator block 12 is supplied with: (a) an external input voltage (Vext) which is distributed to various sub-circuits; (b) "x" test and configuration control signals; (c) "y" static enables control signals; and (d) "z" dynamic enable control signals; where each one of x, y and z may be a different valued integer equal to or greater than one. In response to the application of Vext and the various x, y and z signals, the voltages generator block 12 produces a multiplicity of output voltages (e.g., V1 through Vm) for distribution to, and within, the memory system, and also controls the complex power-on sequence of the voltages generating system. Accordingly, the voltages generator block 12 functions as the basic voltages generator for the DRAM system.
The generated voltages may include reference voltages (e.g., for input/output receivers and bias current and voltage generation in analog circuits) as well as several voltages for supplying different functional blocks of the DRAM with different operating voltages (e.g., VBLH to sense amplifiers or VPP to word line drivers).
In FIG. 1, the controller 14 is supplied with signals from fuses, bond pads and a test mode register and clock signals from an oscillator 18. In addition, the controller is coupled to a voltage detector 19, which is used to sense the presence and/or level of certain of the operating and control voltages. The controller 14 is coupled via "x" wire connections (e.g., w1 through wx) and via "y" wire connections to the voltages generator 12. The "x" wire connections serve to carry configuration and test signals and the "y" wire connections serve to carry static enable signals from the controller 14 to the voltages generator 12. Some of these signals are used to manage the complex power on sequence of the generator system and several test and burn-in modes. Some of the configuration signals supplied to the voltages generator 12 function to adjust some of the output voltages to set up a specified addressing mode or a refresh mode of the memory. Other configuration signals may be used to trim oscillators located in the generator block 12 and/or in other sections of the DRAM. Test mode signals may be used to control the function of selected circuits in the voltages generator block 12 or the functionality of other circuits of the DRAM. In addition, a number of dynamic enable signals are coupled from various memory circuits to the voltages controller.
Thus, numerous wire connections are needed to couple the various test and configuration signals to the voltages generator 12 in order to produce the various configurations and to carry out various tests and functions. In accordance with the prior art, a large number (e.g., N, where N is an integer greater than one) of control lines are coupled between a controller and a voltages generator block to carry a large number (e.g., N) of control signals between the controller and the voltages generator. These control lines have to be routed about the chip. The lines and the spacing between the lines takes up much valuable chip space. This creates a problem because the available space and, in particular, the wiring space is very limited. Hence, due to the limited wiring space, the number of test modes and configurations that can be implemented is limited. This results in severe constraints and problems which are significantly reduced in memory systems embodying the invention.